[PDF] Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization-论文阅读讨论-ReadPaper

摘要

When modern FPGA architecture becomes increasingly complicated, modern FPGAplacement is a mixed optimization problem with multiple objectives, includingwirelength, routability, timing closure, and clock feasibility. Typical FPGAdevices nowadays consist of heterogeneous SLICEs like SLICEL and SLICEM. Theresources of a SLICE can be configured to {LUT, FF, distributed RAM, SHIFT,CARRY}. Besides such heterogeneity, advanced FPGA architectures also bringcomplicated constraints like timing, clock routing, carry chain alignment, etc.The above heterogeneity and constraints impose increasing challenges to FPGAplacement algorithms. In this work, we propose a multi-electrostatic FPGA placer considering theaforementioned SLICEL-SLICEM heterogeneity under timing, clock routing andcarry chain alignment constraints. We first propose an effective SLICEL-SLICEMheterogeneity model with a novel electrostatic-based density formulation. Wealso design a dynamically adjusted preconditioning and carry chain alignmenttechnique to stabilize the optimization convergence. We then propose atiming-driven net weighting scheme to incorporate timing optimization. Finally,we put forward a nested Lagrangian relaxation-based placement framework toincorporate the optimization objectives of wirelength, routability, timing, andclock feasibility. Experimental results on both academic and industrialbenchmarks demonstrate that our placer outperforms the state-of-the-art placersin quality and efficiency.

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