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A Comprehensive Test Pattern Generation Approach Exploiting SAT Attack for Logic Locking

Yadi ZhongUjjwal Guin
Apr 2022
The need for reducing manufacturing defect escape in today's safety-criticalapplications requires increased fault coverage. However, generating a test setusing commercial automatic test pattern generation (ATPG) tools that lead tozero-defect escape is still an open problem. It is challenging to detect allstuck-at faults to reach 100% fault coverage. In parallel, the hardwaresecurity community has been actively involved in developing solutions for logiclocking to prevent IP piracy. Locks (e.g., XOR gates) are inserted in differentlocations of the netlist so that an adversary cannot determine the secret key.Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in[1], can break different logic locking schemes in minutes. In this paper, wepropose a novel test pattern generation approach using the powerful SAT attackon logic locking. A stuck-at fault is modeled as a locked gate with a secretkey. Our modeling of stuck-at faults preserves the property of fault activationand propagation. We show that the input pattern that determines the key is atest for the stuck-at fault. We propose two different approaches for testpattern generation. First, a single stuck-at fault is targeted, and acorresponding locked circuit with one key bit is created. This approachgenerates one test pattern per fault. Second, we consider a group of faults andconvert the circuit to its locked version with multiple key bits. The inputsobtained from the SAT tool are the test set for detecting this group of faults.Our approach is able to find test patterns for hard-to-detect faults that werepreviously failed in commercial ATPG tools. The proposed test patterngeneration approach can efficiently detect redundant faults present in acircuit. We demonstrate the effectiveness of the approach on ITC'99 benchmarks.The results show that we can achieve a perfect fault coverage reaching 100%.